parti-wave/TAV_RGC_World_DiscoverPhysics

TAV RGC World — Deterministic 49-Core Logistic Lattice

A hardware-characterized, finite-precision logistic-map lattice (49 parallel Q1.31 iterators) on an Artix-7 FPGA

This world definition provides a realistic computational substrate based on actual FPGA telemetry from the logistic_bank core on the Arty A7-100T. It implements a 49-core synchronous logistic-map lattice in Q1.31 fixed-point arithmetic (32-bit recurrent state per core), with per-core r values spanning [3.5, 4.0] to tile the period-doubling route to chaos. The state is telemetered as its top 24 bits (x_value[31:8]); the low 8 bits are retained on-chip but not transmitted.

What This World Represents

Unlike purely theoretical or software-simulated worlds, this definition is grounded in measured hardware behavior from four independent cold-start runs (N1, N2, N3, N4). The current reference run is N4: 30 days, 0:00:00 of continuous capture, closed by a pre-scheduled termination on 2026-07-06 with an instrument-generated session certificate.

Key measured properties:

• Cross-run bit-exact determinism. Independent cold-start runs reproduce identical telemetered sequences (24-bit x, full-width n) over their full common prefix: N1 ≡ N2 ≡ N3 ≡ N4. This is the lattice's most-verified property.
• 16 cores have periods short enough to be exactly resolved within the capture window and faithfully through the 24-bit telemetry.
• 33 cores have periods that are only lower bounds, for two compounding reasons: (a) their true period in the 32-bit Q1.31 state space exceeds the observation window, and (b) the 24-bit export drops the low 8 state bits, so an apparent repeat in telemetry is not a confirmed period (distinct 32-bit states can share the same top 24 bits). The partition is therefore an observation/telemetry-resolvability property, not a structural feature of the dynamics. (See the core 04 case study below for this caveat demonstrated live.)
• Strict data integrity: only frames with delta_n = 49 are accepted. The iteration counter n is telemetered at full 32-bit width, so the integrity accounting is exact and unaffected by the x truncation.
• Zero observed single-event upsets across the 30-day N4 run: no configuration or state upset surfaced anywhere in the Δn or orbit data, on hobbyist-grade silicon at sea level.

N4 Reference Run — Session Certificate (2026-06-06 → 2026-07-06)

N4 was closed at exactly 30 days by a pre-scheduled SIGINT; the bridge's automatic session summary is reproduced here as the run's certificate:

Metric	Value
Duration	30 days, 0:00:00
Logistic frames	18,143,975 (0 malformed)
Total heartbeats	18,218,909 (0 lost)
Cores observed	49 / 49
Iteration health	delta_n mean = 49.0, min = 49, max = 49
Average frame rate	7.03 Hz
Stability score	81.2 / 100

The delta_n line is the whole integrity verdict in one row: across a full month of continuous capture, the per-core iteration delta never once deviated from exactly 49.

Witnessed 2^24 Counter Crossing

The N4 window contained the iteration counter's 2^24 carry (n = 16,777,216, reached at day ~27.7). The event was predicted in advance — including which core would export the exact carry row (core 08, since 2^24 mod 49 = 8) — and certified from the captured data:

• Zero delta_n ≠ 49 rows in the 10,001 frames straddling the carry (±5,000);
• 49/49 cores show clean straddles;
• The exact carry row was logged by core 08 as predicted (n = 0x01000000, x_raw24 = 0x49DE3E);
• All telemetry-periodic cores' orbit sets are bit-identical before and after the crossing.

The carry is arithmetic, not an event: the counter is an odometer, and the lattice state marches through it unchanged.

Case Study: Core 04 and the 24-bit Telemetry Caveat

Core 04 (r = 3.5416̄, the lattice's closest core to the 4→8 bifurcation at r ≈ 3.5441) demonstrates the resolved/projected caveat in live data. Three views of one orbit:

• A 6-decimal normalized view of the telemetry shows 4 distinct values;
• The raw 24-bit export shows 6 distinct codes (stable from frame ~200k to end of run, with no step change — consistent with zero upsets);
• The true 32-bit on-chip cycle, computed by a bit-exact software twin of the datapath, is period-8: two of the six 24-bit codes each conceal an LSB-adjacent pair of 32-bit states.

One orbit, three resolutions. The quantized hardware expresses period-8 structure at an r value ~0.0024 before the continuum bifurcation point — real period-doubling microstructure in fixed-point silicon. Standing rule derived from this case: exact-period claims are made on x_raw24, never on the normalized decimal view.

Uncoupledness, Verified Three Ways

Each core's update consumes only its own state and its own r word. This is verified by (a) the RTL source (no neighbor term exists in the update), (b) a solo-core software twin that reproduces the telemetered sequences bit-exactly — impossible if any inter-core coupling existed, since a single injected LSB would diverge chaotic cores within ~100 frames — and (c) the month-long coexistence of bit-exact period-locked cores adjacent to chaotic cores, which no nonzero coupling permits. The lattice is a synchronous, uncoupled bank of 49 independent maps; sharing a clock is not sharing state.

Reproducibility — scope of the claim

Reproducibility is asserted for the telemetered x observable (top 24 bits of the 32-bit Q1.31 state) and for the full-width n counter. The recurrent state is 32 bits; the export transmits the high 24 of those bits and drops the low 8 (noise-dominated). Identical cold-start runs therefore reproduce the same telemetered x sequences bit-for-bit, but this is reproducibility of the 24-bit observable, not a claim about the 8 untransmitted state bits. This is the strongest statement the telemetry can support, and it is the one made here.

Data Integrity and the Capture-Onset Transient

Frame integrity is enforced by a single rule: only frames carrying a global iteration delta of exactly delta_n = 49 are accepted.

Steady-state frame corruption is zero. All rejected frames occur during the capture-onset framer-lock transient — the interval before byte/frame alignment is acquired on the free-running UART stream — and they never recur once lock is established. The FPGA emits frames continuously and does not wait for the host; when the host attaches, it drops into a live stream with pre-existing bytes in the transmit FIFO and OS serial buffer. Until two consecutive sequence-numbered frames produce a valid delta_n = 49, each misaligned read fails the integrity test and is rejected. Once lock is acquired it is retained for the remainder of the capture.

Empirically the transient is a fixed-depth flush in N1–N3: exactly 49 frames rejected in every run, independent of capture length — one per core, consistent with a single stale 49-core readout sweep being cleared before lock. N4's hardened bridge reported 0 malformed frames over the full 30-day capture at the instrument layer; the loader-level onset accounting for N4 (whether the exactly-49 pattern recurs under the hardened framer) is being confirmed against the final CSV in the post-close audit and this section will be updated with the result.

These onset frames are excised by the integrity rule at the loader, not by modifying the instrument during a live capture. A rejected frame appearing after lock would be a genuine anomaly; none has been observed across any run.

Run Provenance

• N1 — 48 hours; planned endpoint. First determinism anchor.
• N2 — 4,000,000 frames; planned endpoint (frame-count watcher). Original reference run, superseded by N4.
• N3 — 8,000,000-frame target; terminated early by a host-side port conflict (a second consumer attached to the UART during bridge development). Its captured prefix remains bit-identical to the other runs; its ending is documented here as provenance, and the one-owner port rule adopted afterward is why N4 completed.
• N4 — 30 days / 18,143,975 frames; pre-scheduled termination with automatic certificate. Current reference run.

Current Status

• N4 is the reference run (superseding N2). The final N4 CSV (1.3 GB) is the canonical analysis artifact.
• Cross-run determinism is verified bit-for-bit across all four runs over their common prefixes.
• The 16/33 resolved/projected partition is reproducible across runs; N4's longer window is being re-audited post-close, and any promotions from "projected" to "resolved" will update the world definition. The partition remains an observation limit, not a structural bound.
• A follow-on run (N5) is planned: a single-parameter retune of one core's r word, with a pre-registered orbit prediction to be graded against capture.

Full methods and analysis are documented in the accompanying tav_rgc_world.yaml and supporting scripts.

Files Included

• tav_rgc_world.yaml — Core world definition (v1.1)
• tav_rgc_world.py — Python loader
• example_load_run.py — Example loader with integrity filtering
• compare_all_runs.py — Comparison tool across runs
• rgc_integrity.py — Capture-onset lock detection and frame partitioning
• rgc_period_census_v1.py — Per-core period census (note: census basis is the normalized view; exact-period verdicts require x_raw24 — see core 04 case study)
• n4_crossing_certificate.py — 2^24 carry-crossing certificate generator
• README.md — Usage documentation

Quick Start

from tav_rgc_world import RGCWorld

world = RGCWorld("tav_rgc_world.yaml")
print(world.summary())

resolved = world.get_resolved_cores()
projected = world.get_projected_cores()